BIOS Setup

Auto Configuration
Chipset I/O Wait States
Chipset Special Features
Command per Cycle

Delayed Read Request Expiration
Extended I/O Decode
Fast Decode Enable
Host Bus Fast Data Ready
ICH Decode Select


PIIX4 SERR#
Pipelined Function
System Performance
Bit I/O Recovery Time
Bit I/O Recovery Time

Bit ISA I/O Command WS
Bit ISA Mem Command WS
AT Cycle Wait State
Back to Back I/O Delay
Bus Request when FIFO is
Byte Merge Support
CPU Dynamic-Fast-Cycle
CPU Read PCI Retry
CPU-to-PCI 6 DW FIFO
CPU-to-PCI Bridge Retry

CPU to PCI Burst Memory Write
CPU-to-PCI FIFO Cleaning
CPU-to-PCI IDE Posting
CPU to PCI POST/BURST
CPU-to-PCI Read Buffer
CPU to PCI Read Burst
CPU-to-PCI Write Buffer
CPU-to-PCI Write Latency
CPU-to-PCI Write Posting
Delayed Transaction

DRAM-to-PCI 24 DW FIFO
DRAM to PCI RSLP
Early PCI Bus Request
Extra AT Cycle WS
Fast AT Cycle
Fast Back-to-Back
Fast Frame Generation
I/O Posted Write Buffer
I/O Recovery Time
L2 to PCI Read Buffer

Max PCI Burst Size
Passive Release
PCI1 to PCI0 Access
PCI#2 Access #1 Retry
PCI Pipeline
PCI Post-Write Fast
PCI-to-CPU Write Buffer
PCI to CPU Write Pending
PCI-To-CPU Write Posting
PCI-to-DRAM 24 DW FIFO

PCI to DRAM Buffer
PCI-to-DRAM Bursting
PCI-to-DRAM FIFO Cleaning
PCI-to-DRAM Pipeline
PCI-to-DRAM Posting
PCI-to-DRAM Prefetch
PCI to ISA Write Buffer
PCI-to-L2 Checkpoint
PCI-to-L2 Read Wait States
PCI to L2 Write Buffer

PCI-to-L2 Write Wait States
PCI-to-PCI Posting
ROM Wait States
USB Passive Release
Write Post During I/O Bridge Access
Содержание раздела

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