BIOS Setup




Глава 04


Drive NA before BRDY
Extended CPU-PIIX4 PHLDA#
Gate A20 Option
Graphic Posted Write Buff
IBC DEVSEL# Decoding
LOCK Function
NA Delay
NA# Enable
NA# On Single Write Cycle
Negate LOCK#
Single ALE Enable
Stop CPU when PCI Flush
Backoff Processor
Base I/O Address
Branch Target Buffer
CPU ADS# Delay 1T or Not
CPU BIST Enable
CPU Drive Strength
CPU Fast String
CPU Line Read Multiple
CPU Read Multiple Prefetch
I/O Space Access
Processor Number Feature
3.1. CPU Speed
CPU Host Clock Select
CPU Ratio
CPU Speed
CPU Vcore
SEL 100/66# Signal
Speed Error Hold
Turbo Frequency
Turbo Mode (75 MHz)
Memory Current
4.1. ECC, Parity
CPU Level 2 Cache ECC Check
Data Integrity (PAR/ECC)
DRAM Data Integrity Mode
DRAM ECC/PARITY Select
Memory Parity/ECC Check
Single Bit Error Report








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