5.1. Арбитраж, Bus-Master
Arbitration Priority
CPU Priority
DMA/ISA Master Before PCI
Master Priority Rotation
PCI Bus Arbitration
PCI Arbiter Mode
Arbiter Priority on HB1
Bus Mastering
CPU Mstr DEVSEL# Time-out
CPU Mstr Fast Interface
CPU Mstr Post-WR Buffer
CPU Mstr Post-WR Burst Mode
Enable Master
Master Prefetch And Posting
Master Retry Timer
PCI Bus Parking
PCI Master 0 WS Write
PCI Master Access to ISA
PCI master accesses shadow RAM
PCI Master Write Ping-Pong
PCI Master Read Prefetch
PCI Mstr Burst Mode
PCI Mstr DEVSEL# Time-out
PCI Mstr Fast Interface
PCI Mstr Post-WR Buffer
Preempt PCI Master Option
Shared PCI Master Assignment
State Machines
Stop CPU at PCI Master
5.2. Все о PCI-шине
PCI 2.1 Support
PCI Clock Frequency
PCI Dynamic Decoding
PCI Latency Timer (PCI Clocks)
PCI Parity Check
PCI Preempt Timer
Peer Concurrency
SERR#
ISA Bus Clock
ISA Slave Wait States